1. Field of the Invention
This invention relates generally to ring oscillator circuits and, in particular, to a ring oscillator or VCO circuit that provides an improved level of noise rejection for noise originating from both the voltage supply and ground.
2. Description of the Related Art
High-speed digital circuits such as microprocessors and memories often employ a phase-locked loop (PLL) circuit to suppress timing skews between the on-chip clock and the system clock. PLL circuits typically include a voltage-controlled oscillator (VCO) circuit to generate a periodic digital signal. FIG. 1 shows a conventional VCO circuit 100. The VCO 100, which is a type of ring oscillator, and consists of N stages of differential inverters 110 with the output of the Nth stage connected back to the input of the first stage. The VCO circuit 100 generates an output signal VCO—out, which is a periodic digital signal having a frequency that is adjustable by varying the voltage of the frequency control signal Vctrl.
The PLL circuit is typically fabricated on the same integrated circuit as the digital circuit and as a result, the switching noise generated by the digital circuit is coupled to the PLL, including the VCO 100. The switching noise is coupled to the PLL circuit through various sources, including the voltage supply VDD, the ground GND and the substrate. The coupling of noise to the VCO 100 causes the output signal VCO—out to suffer from jitter (i.e., rapid variations in phase), thereby reducing the accuracy of the PLL.
A conventional approach to reducing the effect of switching noise is to construct the VCO 100 with differential, rather than single-ended, inverters 110 so that the switching noise is rejected by the inverters as common-mode noise. However, under the large-signal conditions under which most VCOs operate, the differential inverters 'of the VCO may function as a mixer so as to combine the common-mode noise with the differential signal. Consequently, despite its differential operation, the VCO 100 at least partially couples the switching noise to its output.
Another conventional approach is to isolate the inverters from the noise source by placing a high-impedance current source between the noise source and the inverter, as shown in FIGS. 2 and 3. FIG. 2 shows a differential inverter 210 including n-type MOSFET input transistors 211 and 212 and p-type MOSFET load transistors 213 and 214 connected in a conventional differential inverter configuration. The load transistors 213 and 214 are diode-connected with the gate of the transistor connected to the drain. The differential inverter 210 also includes a current source 216 placed between ground and the input transistors 211 and 212. The current source 216 reduces the coupling of noise from ground because of its high impedance relative to the impedance of the ground. Similarly, FIG. 3 shows a differential inverter 310 including PMOS input transistors 311 and 312 and n-type MOSFET load transistors 313 and 314. The differential inverter 310 also includes a current source 315 placed between the voltage supply VDD and the input transistors 311 and 312. The current source 315 reduces the coupling of noise from the voltage supply VDD because of its high impedance relative to the impedance of VDD.
A disadvantage of the differential inverters 210 and 310 is that they are capable of rejecting noise from only one of the potential switching noise sources VDD and ground, but not both. Consequently, switching noises originating from the other supply (i.e., VDD for the differential inverter 210 and ground for the differential inverter 310) can still affect the output of the differential inverter, thereby causing jitter in the output signal VCO—out.
In view of the shortcomings of these approaches, it is an object of the present invention to provide a VCO circuit with an improved level of noise rejection for noise originating from both the voltage supply and ground, i.e., an improved power supply rejection ratio (PSRR).